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| stlc3080 subscriber line interface circuit monochip slic suitable for public applications implementes all key features of the borsht function dual control mode configuration: slave mode or automatic activation mode. soft battery reversal with pro- grammable transition time on hook transmission loop start/ground start feature with progr. threshold low power dissipation in all oper- ating modes automatic dual battery operation integrated ring trip detection with automatic and syncronised ring disconnection metering pulse injection surface mount package three relay drivers for ring and testing -40 to +85c operating range description the stlc3080 is a slic device suitable for a wide range of applications: public (co), transmis- sion (dlc) and private (pabx). the slic pro- vides the standard battery feeding with full pro- grammability of the dc characteristic. in particular two external resistors allow to set the limiting cur- rent value (up to 50ma) and the value of the re- sistive feeding when not in constant current re- gion. january 2004 ? bgnd vreg iltf d0 d1 d2 r0 r1 rel1 rs zac iref v cc ring d98tl305b det gdk/al csin cac agnd crev csvr relr rel0 logic interface & decoder supervision commands line status ilt line interface ill tip rt1 rt2 crt reference & bias switching dc processor + ac+ dc ac dc rlim rth zb tx v dd vbat base rdc ac processor rgnd rx zac1 csout ttxin pcd res mode ckring block diagram tqfp44 (10 x 10) ordering number: stlc3080 1/23
csout rel1 csvr ttxin d98tl306a 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 12 13 14 15 16 csin d0 d1 d2 r0 r1 res vdd vcc crt rel0 relr rgnd vbat tx zb rs zac zac1 rx cac rdc iltf rt2 rt1 agnd rth rlim iref crev base vreg bgnd ring tip pcd mode ckring det gdk/al pin connection absolute maximum ratings symbol parameter value unit v bat battery voltage -80 + v cc to +0.4 -80 + v rel to + 0.4 v v v cc positive supply voltage -0.4 to +7 v v dd control interface supply voltage -0.4 to +7 v i rel current into relay drivers 80 ma a/r/bgnd agnd respect bgnd respect rgnd -2 to +2 v operating range symbol parameter value unit t opt operating temperature range -40 to +85 c v cc positive supply voltage 4.75 to 5.25 v v dd control interface supply voltage 3 to 5.25 v v bat battery voltage if vrel > v cc -73 to -15 -78 + v rel to -15 v v a/r/bgnd agnd respect bgnd respect rgnd -0.3 to +0.3 v pd (70) max. power dissipation @ tamb = 70c 1.1 w pd(85) max. power dissipation @ tamb = 85c 0.9 w thermal data symbol parameter value unit r th j-amb thermal resistance junction to ambient typ. 60 c/w stlc3080 2/23 pin description pins name description 1 csout chip-select for output control bits det and gdk . active low. (*) 2 csin chip-select for input control bits latches d0 d1 d2 r0 r1 . active low. (*) 3 d0 control interface input bit 0. (*) 4 d1 control interface input bit 1. (*) 5 d2 control interface input bit 2. (*) 6 r0 relay driver 0 command. active high. (*) 7 r1 relay driver 1 command. active high. (*) 8 res reset input; active low. 9v dd control interface power supply. v dd = 3.3v or v dd = v cc . 10 v cc positive power supply (+5v). 11 crt ring-trip time constant capacitor. 12 rel1 relay 1 driver output. 13 rel0 relay 0 driver output. 14 relr ringer relay driver output. 15 rgnd relay drivers ground. 16 v bat negative battery supply. 17 tx 4 wires output stage (transmitting port). 18 zb cancelling input of balance network for 2 to 4 wires conversion. 19 rs protection resistors image. the image resistor is connected between this node and zac. 20 zac ac impedance synthesis. 21 zac1 rx buffer output/ ac impedance is connected between this node and zac. 22 rx 4 wires input stage (receiving port). a 100k external resistor must be connected to agnd to bias the input stage. 23 ttxin metering signal input (ac) and line voltage drop programming (dc). if not used must be connectd to agnd. 24 cac ac feedback input/ ac-dc split capacitor is connected between this node and iltf. 25 rdc dc current feedback input. the rdc resistor is connected between this node and iltf. 26 iltf transversal line current image. 27 rt2 input pin to sense ringing current , for ring-trip detection. 28 rt1 input pin to sense ringing current , for ring-trip detection. 29 agnd analog ground. 30 rth off-hook threshold programming pin. 31 rlim limiting current programming pin. 32 iref voltage reference output to generate internal reference current. 33 crev reverse polarity transition time programming. 34 csvr battery supply filter capacitor. 35 base driver of the external transistor. connected to the base. 36 vreg regulated voltage. provides the negative supply to the power line drivers. it is connected to the emitter of the external transistor. 37 bgnd battery ground. 38 ring b wire termination output. ib is the current sunk into this pin. 39 tip a wire termination output. ia is the current sourced from this pin. 40 pcd power cross detection input 41 mode interface control mode selection. 42 ckring clock at ringing frequency for relay synch and time reference for automatic activation 43 det off-hook and ring-trip detection bit. tri-state output/active low. 44 gdk/ al ground-key/alarm detection bit. tri-state output. active low. * input pins provided with 15 a sink to agnd pull-down. stlc3080 3/23 a parallel interface allow to control the operation of stlc3080 through a control bus: - d0 d1 d2 latched input bits defining the slic operation mode - r0 r1 latched input bits (active high) drive the test relays. - det and gdk/ al , tri-state outputs, signal the status of the loop: on/off-hook and ground-key. pin gdk/ al goes low also when the device thermal protection is activated or a line fault (tip to ring, tip and/or ring to ground or vbat) is detected (flowing current 7.5ma). - csin: chip select for input bits, active low, strobes the data present on the control bus into the internal latch. - csout: chip select for output bits ; active low , when high det and gdk/ al goes tri-state. d0 d1 d2 r0 r1 csin and csout inputs are provided with a 15 a pull-down current to prevent uncontrolled conditions in case the control bus goes floating. according to the above table, 8 operating modes can be set: 1) power-down. 2) stand-by. 3) active n.p. 4) active r.p. 5) ringing (with slic active n.p.). 6) ringing (with slic active r.p.). 7) ground start. 8) high impedance feeding. power-down it?s an idle state characterised by a very low power consumption; any functionality is disabled; only relays rel0 and rel1 can be driven by proper setting of bits r0 and r1. it can be set during out of service periods just to reduce the power consumption. it is worth noticing that two other conditions can set the slic in idle state but with some differences as reported in the table: idle state rel0/1 drive det gdk/ al power down enable disable disable reset disable disable disable thermal alarm enable low low stand-by. mode selected in on-hook condition when high immunity to common mode currents is needed for the det bit. to reduce the current consumption, ac feedback loop is disabled and only det and gdk/ al de- tectors are active. dc current is limited at 16ma (not programma- ble); feeding characteristic shown in fig. a. the voltage drop in on-hook condition is 7.8v. active mode selected to allow voice signal transmission. when in active mode the voltage drop in on- hook condition is 7.8v in order to allow proper on- hook transmission (fig. b). control interface slave mode (mode=low). inputs operating mode outputs r0 r1 d0 d1 d2 det (active low) gdk / al (active low) x x x x x x x x 0/1 x x x x x x x x x x 0/1 0 0 0 0 1 1 1 1 x x 0 0 1 1 0 0 1 1 x x 0 1 0 1 0 1 0 1 x x power down stand-by active n.p. active r.p. ringing (with slic active n.p.) ringing (with slic active r.p.) ground start high impedance feeding rel 0 (on = 1, off = 0) rel 1 (on = 1, off = 0) disable off/hk off/hk off/hk ring/trip ring/trip off/hk off/hk def by d0-d2 def by d0-d2 disable gnd-key gnd-key gnd-key disable disable gnd-key disable def by d0-d2 def by d0-d2 16ma r feed = 2r p d98tl307 v bat -7.8v i v figure a: stlc3080 dc characteristic in stand-by mode. stlc3080 4/23 resistive region is programmable by means of external resistor r dc , limiting current can be se- lected by r lim resistor. concerning ac characteristic the stlc3080 allows to set 2w termination impedance by means of one external scaled impedance that may be complex. two to four wire conversion is provided by an exter- nal network. such network can be avoided in case of application with comboii, in this case the two to four wire conversion is implemented inside the comboii by means of the programmable hybal fil- ter. when in active mode it is also possible to per- form battery reversal in soft mode (with program- mable transition time) without affecting the ac sig- nal transmission. ringing when ringing mode is selected the stlc3080 activates the ring relay injecting the ringing signal on the line. as the ring trip is detected the logic in- dicator det is set low and the ringing is automat- ically disconnected without waiting for the card controller command (auto ring trip). det remains latched low untill the operative mode is modified. if required , the ringing relay drive signal relr can be synchronised to a clock applied to ckring input. this clock is derived from the ringing signal with proper time delay, according to the activation/de- activation time of the relay. relr is activated on the low level of ckring clock. the duty cycle of ckring can be modified in order to activate the relr when required: ckring low must last 1 s minimum. if the synchronisation is not required, ckring in- put must be steadily kept low. all the stlc3080 relay drivers are open drain with the source connected to the rgnd pin. each relay drivers integrates a protection structure that allows to avoid external kick - back diodes, using both 5v or 12v relays. the ring trip circuit and its behaviour is described in appendix d. ground start. this mode is selected when the slic is adopted in a system using the ground start feature. in this mode the tip termination is set in high imped- ance (100k ? ) while the ring one is active and fixed at vbat +4.8v. in the case of connection of ring termination to gnd the sinked current is limited to 30ma. when ring is connected to gnd both off-hook and ground-key detectors become active. power dissipation in this mode with a -48v battery voltage is 100mw high impedance feeding. as stand-by, this mode is set in on-hook condi- tion, with further reduced power consumption. higher power efficiency turns back a lower immu- nity of the off-hook detector to line common mode currents. the dc feeding shows a constant current charac- teristic (i lim = 17ma) followed by a resistive range with an equivalent series resistance r feed = 1600 ? + 2rp. thermal protection circuit is still active, preventing the junction temperature, in case of fault condi- tion, to exceed 150c in high impedance feeding most of the circuit is switched off, only the circuit, dedicated to off- hook detection, is powered. this allows to reduce the total power consumption in on-hook to 30mw (typical). the off-hook detection threshold is not program- mable but defined at a fixed i det hi = 8ma(max.) i lim [20 50ma] r feed = r dc 5 +2r p r feed = 2r p v bat v bat -7.8v i v figure b. stlc3080 dc characteristic in active mode. 17ma r feed = 1600 ? +2r p d98tl373 v bat -0.8v i v figure c. stlc3080 dc characteristic in high impedance feeding stlc3080 5/23 control interface automatic activation mode (mode=high). inputs operating mode (mode = high) outputs r0 r1 d0 d1 d2 res det gdk / al x x 0 0 0 1 power down disable disable x x 0 0 1 1 ringing ring-trip disable x x 0 1 0 1 on-hook transmission reverse polarity off-hook fault fault x x 0 1 1 1 on-hook transmission direct polarity off_hook fault fault x x 1 0 0 1 active direct polarity (default) off_hook fault fault x x 1 0 1 1 active direct polarity (default) off_hook fault fault x x 1 1 0 1 active reverse polarity off_hook fault fault x x 1 1 1 1 active direct polarity (default) off_hook fault fault 0/1xxxx1 r0 = 0/1: rel0 = off/on (1) (1) x 0/1 x x x 1 r1 = 0/1: rel1 = off/on (1) (1) xxxxx0power down; rel0/1 = off disable disable det: on/off hook signalling ; together with gdk/ al it is set low also in case of thermal alarm or ground-key. gdk/ al : thermal alarm or ground-key signalling (1) : det and gdk/ al signalling function is related to d0,d1,d2 and it doesn?t depend on r0 and r1 setting. as in slave mode the control is performed through a parallel bus, with independent chip se- lects, csin and csout, for inputs and outputs. in automatic activation, once active mode is se- lected the device automatically selects the proper operating mode (active, stand by or h.i. feeding) depending on the loop status in order to optimise the power consumption. in order to guarantee the proper behaviour of the internal state machine the "ckring" signal must be always applied, this signal in fact is used to gen- erate the "wtime" delay (see appendix) necessary to properly perform automatic state change. power-down it?s an idle state characterised by a very low power consumption; any functionality is disabled; only relays rel0 and rel1 can be driven by proper setting of bits r0 and r1. it can be set during out of service periods just to reduce the power consumption. it is worth noticing that two other conditions can set the slic in idle state but with some differences as reported in the table: idle state rel0/1 drive det gdk/ al power down enable disable disable reset disable disable disable thermal alarm enable low low ringing when ringing mode is selected the stlc3080 activates the ringing relay injecting the ringing sig- nal on the line. as a ring-trip is detected the logic indicator det is set low and the ringing relay is automatically switched-off without waiting for the card control- ler command (auto ring-trip). det remains latched low until the operative mode is modified. ringing relay drive signal relr must be synchro- nised to a clock applied to ckring input. this clock is derived from the ringing signal with proper time delay, according to the activation / deactivation time of the relay. relr is activated on the low level of ckring clock. the duty cycle of ckring can be modified in order to activate the relr when required: ckring low must last 1 s minimum. all the relay drivers are open-drain with the source connected to rgnd pin. each relay driver integrates a protection structure to avoid external kick-back diodes using both 5v or 12v relays. the ring trip circuit and its behaviour is described in appendix d. on-hook transmission. sets the slic for conversation even though the line is in on-hook; it is required for on/hook transmis- sion purposes; active mode cannot support a con- versation when the line is in on-hook as it automat- ically turns in high impedance feeding. active. the relevant feature of this setting is that when active mode (d0d1d2=1xx) is set by the exter- nal control , internally, the device is able to select between three operative states according to the status of the line: stlc3080 6/23 - high impedance feeding : entered after a power-on reset or 1xx word, this status is set during steady on/hook condition; most of the circuitry is idle and only a low power off-hook detection circuit is kept alive. direct polarity only is assumed , independently of the selected one. to minimise the power consumption the off-hook de- tection circuit has low common mode current rejection. - stand by notice that in stand-by state the off-hook detec- tor is sensitive only to the transversal component of the line current with high immunity to common mode disturbances; this performance implies an increasing in power consumption: for that reason stand-by is not used as a quiescent state. - active state gets operative for conversation af- ter an off-hook validity check performed in stand-by state, set after any off-hook detected in high impedance feeding. if the off-hook condition is confirmed in stand by, active mode is set ; if not (in case of spurious de- tection), false activation is prevented, and high impedance feeding is resumed. in order to have the device falling back in hi-feed- ing mode after the line is back in on-hook condi- tion. it is necessary to select as input state the ac- tive direct polarity mode (default). during active state on/off-hook status will af- fect in real time det signalling bit. in order to allow pulse-mode dialling, once ac- tive state is set, it cannot be changed by fast on- hook , but it is turned back to high impedance feeding only if an on-hook condition lasts longer than 128 x ckring period. automatic activation (and deactivation) is based on an internal state-machine which is clocked by a free running internal oscillator. a detailed description is reported in the appendix a. dual battery configuration stlc3080 is also meant for low power consump- tion systems using dual battery solution. it is suf- ficient to connect the collector of the external tran- sistor, through a diode, to the reduced battery (see fig. 2 for single battery solution and fig. 3 for dual battery solution). the activation of the batteries is automatic, only depending on the dc load at the ring and tip terminals; no controllers action is required. protection circuit - suggested protection circuit is based on pro- grammable trisils (like lcp1511/2) as shown in fig.2 and fig. 3, and the surge current is limited by the resistors rpt2 and rpr2, which are ptc types , protecting the device against both lightning and power-cross. - additionally, stlc3080 is provided with the pcd input to directly monitor overvoltages ap- plied to the line wires. when the current injected into pcd exceeds a threshold of 320 a (+/- 30%) , det and gdk/ al are set low signalling a fault condition. no change on the slic mode is performed. voltage threshold is defined by proper value of the series resistors (see fig.1) this circuit gives the possibility to protect the de- vice against power crosses through a relay in- stead of ptcs; once the fault condition is de- tected the controller drives this relay disconnecting the slic from the line terminals. metering pulse injection stlc3080 provides external pins and compo- nents for metering pulse injection. ttxin pin is the input for the 12khz or 16khz metering pulse injection. this pin also provides a dc constant current source that is injected into the external rda resistor (typ. 10k ? to obtain 2.2vrms on 200 ? ) connected between ttxin pin and agnd. the voltage drop across tip and ring line ampli- fiers and, consequentally the ac swing available. when metering pulse injection is not used and voltage drop is not required, ttxin must be shorted to agnd and rttx, rda and cttx ex- ternal components must be removed. the ttx cancellation is obtained through an external rttx and cttx network connected between ttxin and cac pins. fault detection the device provides current sense on tip and ring wires that allow to detect longitudinal dc current (i ll ). when this i ll current becomes higher than a threshold (see detectors table in- side electrical characteristics) a fault indication is provided on det and gdk pin (both outputs be- come low). the fault indication is active till the fault cause persists. with this circuit the following fault condition can be detected. tip to vb1 tip to gnd ring to vb1 ring to gnd ring to tip to vb1 vcc r r tip ring pcd det gdk/al d98tl385 csout ith figure 1. stlc3080 7/23 when a fault is detected the line current is limited in order to avoid any damage on the device itself and also on the external transistor. miscellaneous - thermal overload: the integrated thermal pro- tection is activated when tj reaches 150c typ.; the slic is forced in power-down mode, det and al are set low. the relr relay driver is turned off while it is still possible to control rel0 and rel1 through r0 and r1 inputs. - one low cost external transistor allows to re- duce the power dissipated in the slic itself al- lowing the use of extreme small size package (tqfp44). the external transistor size/package can be selected depending on the max. power requested by the particular application. - the slic supports loop start lines and gives the possibility to set loop current indicator threshold by means of one external resistor. external components list to set the slic into operation the following pa- rameters have to be defined: - the dc feeding resistance "rfeed" defined as the resistance of the traditional feeding sys- tem (most common rfeed values are: 400, 800, 1000 ohm). - the ac slic impedance at line terminals "zs" to which the return loss measurements is re- ferred. it can be real (typ. 600 ohm) or com- plex. - the equivalent ac impedance of the line "zl" used for evaluation of the trans-hybrid loss performance (2/4wire conversion). it can be a complex impedance. - the value of the two protection resistors rp in series with the line termination. - the reverse polarity transition time defined as " ? v tr / ? t". - the constant current limit value "i lim ". - rth: sets the off/hook detection threshold once, the above parameters are defined, it is possible to calculate all the external components using the following table. external components name function formula typical value cvcc positive supply filter 100nf 20% cvb battery supply filter 100nf 20% 100v r ref (*) internal current reference programming resistor i ref = 1.16 r ref 30.1k ? 1% c svr battery ripple rejection capacitance c svr = 1 2 ? fp ? 1.3m ? 100nf 10% 100v @ fp = 1.22hz c rt ring trip capacitance see appendix d 470nf 20% 6v @ 25hz r dc dc sinthesized resistance programming resistor r dc = 5[r feed -2rp] r dc 1k ? 1.5k ? 1% c ac ac/dc splitter capacitance c ac = 1 2 ? fsp ? r dc 10 f 20% 15v @ fsp = 10hz r s protection resistor image r s = 25 ? 2rp 2.5k ? 1% zac 2 wire ac impedance z ac = 25[zs - 2rp] 12.5k ? 1% za slic impedance balancing network za = 25 ? zs 15k ? 1% zb line impedance balancing network zb = 25 ? zl 15k ? 1% c comp ac feedback compensation capacitance c comp = 2 2 ? fo [100 ? rp] 220pf 20% @ fo = 250khz rr feeding resistance for ring injection 400 ? 600 ? 2w rs1 sensing resistor for ring trip 1000 ? rr 600k ? 1% rs2 sensing resistor for ring trip 1000 ? rr 600k ? 1% rt feeding resistance for ring injection 0 ? 0 ? q ext external transistor (1) bd140, mjd32 rpt1 line series resistor 20 ? rpr1 line series resistor 20 ? 20 ? 1/4w 1% stlc3080 8/23 name function formula typical value r lim (*) current limiting setting resistor r lim = 10 3 ? 1.16 i lim 23.2k ? 58k ? 51.1k ? 1% r th (**) off/hook detection threshold setting resistor. r th = 200 ? 1.16 i th 21.1k ? 77.3k ? 26.1k ? 1% c rev polarity reversal transition time programming c rev = k ? v tr ? t ; k = 1 3750 47nf for 5.67v/ms rda output voltage drop adjustment rda = ? drop ? 20k ? 9.6 ? ? drop 10k ? ( ? drop = 3.2v) (2) r1, r2 power cross detection 240k ? (3) r ttx teletax cancellation resistor r ttx = 12.5 ? [re (zl ttx ) + 2r p ] 3.75k ? c ttx teletax cancellation capacitor c ttx = 1 ( 12.5 ? i m ( zl ttx ) ? 2 ? f ttx ) rpt2 protection resistor 8 ? rpr2 protection resistor 8 ? d1 overvoltage protection 1n4448 d2 dual battery operation 1n4448 ch trans-hybrid loss frequency compensation ch = ccomp 220pf 30% notes: (1) transistor characteristics: h fe 25, i c 100ma, v ceo 60v, f t 20mhz in all operating range (ic from 1 to 100ma). pdiss depends on application, see appendix. for smd application possible alternatives are mjd350 in d-pack or bcp53 in sot223 (2) typical value needed for 2.2vrms metering pulse level, if no metering rda = 0 ? . (3) these resistors are needed to activate the power cross detection circuit, they should withstand the typical lighting voltag e. if the power cross detection is not needed r1, r2 can be avoided. (*) r ref and rlim should be connected close to the corresponding pins of stlc3080. avoid any digital line or high voltage swing line to pass close to i ref and r lim pins. eventually screen these pins with a gnd track. (**) inside the formula the coefficient 1.16 must be changed to 1.20 if the selected value of i th is lower than 5ma. 20 ? 1/4w 1% external components (continued) 20 ? 1/4w 1% stlc3080 9/23 rs zac za zb ccomp tx rs zac zb tx control interface d0 d1 d2 r0 r1 v cc agnd bgnd rel1 cac rdc cac + crt crt iref rref tip rpt1 lcp 1511 rpr1 rpt2 rpr2 ring la vrel lb vb- vreg base crev crev vb- vring rr d98tl308c csvr (1) this components are needed only for power cross indication (normally not used). (2) components needed only for metering pulse injection. stlc3080 d0 d1 d2 r0 r1 det det gdk/al csin csin iltf rdc rlim rlim rth rth csvr rs2 rt2 rs1 rt1 rt relr rel0 v cc cv cc v dd rgnd v dd qext ch vbat d1 zac1 rx rx vb- csout csout ttxin ttx rda rttx cttx cvb pcd res res ckring ckring mode mode gdk/al r2(1) r1(1) (2) figure 2. typical application diagram. rs zac za zb ccomp tx rs zac zb tx control interface d0 d1 d2 r0 r1 v cc agnd bgnd rel1 cac rdc cac crt crt iref rref tip rpt1 lcp 1511 rpr1 rpt2 rpr2 ring la vrel lb vb2 vreg base crev crev vb- vring rr d98tl310c csvr (1) this components are needed only for power cross indication (normally not used). (2) components needed only for metering pulse injection. stlc3080 d0 d1 d2 r0 r1 det det csin csin iltf rdc rlim rlim rth rth csvr rs2 rt2 rs1 rt1 rt relr rel0 v cc cv cc v dd rgnd v dd qext ch vbat d2 zac1 rx rx vb- csout csout ttxin ttx rda rttx cttx d1 vb- pcd res res ckring ckring mode mode gdk/al gdk/al r2(1) r1(1) (2) cvb + figure 3. typical dual battery application diagram. stlc3080 10/23 electrical characteristics (test condition, unless otherwise specified: v cc = 5v, v dd = 3.3v, v b- = -48v, agnd = bgnd = rgnd, t amb = 25c). note: the limits below listed are guaranteed with the specified test condition and in the 0 to 70c tem- perature range. performances over -40 to +85c range are guaranteed by product characterisation. symbol parameter test condition min. typ. max. unit fig. ac characteristics zil long. impedance each wire 40 ? i il long. current capability ac h.i. feeding per wire (on- hook) 5mapk standby or active per wire (on-hook) 13 mapk active per wire (off- hook). i t = transversal current 80 -i t mapk l/t long. to transv. np with nominal r p at 300hz 60 db c5 np with nominal r p at 1020hz 60 db np with nominal r p at 3400hz 55 db t/l transv. to long np with nominal r p at 300hz 37 db np with nominal r p at 1020hz 40 db np with nominal r p at 3400hz 40 db 2wrl 2w return loss. 300 to 3400hz 22 db c6 thl trans-hybrid loss. 1020hz; 20log |vrx/vtx| 30 db c2 ovl 2w overload level active mode at line terminals on ref. imped. 3.2 dbm txoff tx output offset -200 200 mv g24 transmit gain abs. 0dbm 1020hz -12.38 -12.02 db c4 g42 receive gain abs. 0dbm 1020hz 5.74 6.1 db c1 g24fq tx gain variation vs. frequency rel. 1020hz, 0dbm 300 to 3400hz -0.1 0.1 db g42fq rx gain variation vs. frequency rel. 1020hz, 0dbm 300 to 3400hz -0.1 0.1 db g24lv tx gain variation vs. level f = 10120hz, input level from 3dbm to -40dbm -0.1 0.1 db g42lv rx gain variation vs. level -0.1 0.1 db v2wp idle channel noise at line terminals psophometric, active on hook -82 -78 dbmp c8 v4wp idle channel noise at tx port psophometric, active on hook -90 -84 dbmp c7 thd total harm. dist. 2w-4w, 4w- 2w 0dbm, 1khz il = 20 to 45ma -50 db g ttx transfer gain v ttx = 100mv rms @ 16khz g ttx = 20log ? ? ? v l v ttx ? ? ? with r l = 200 ? 14.5 db thd (ttx) ttx harmonic distortion 2.2v rms = on 200 ? 3% dc characteristics (ttx pin connected to ground) vlohi line voltage il = 0, h.i. feeding 47 47.4 47.8 v vlo line voltage il = 0, sby/active/on- hook 38.9 39.9 40.9 v ilims short circ. curr. r loop = 0, sby 14 16 18 ma ilimb short circ. curr. r loop = 0, h.i. feeding 11 17 20 ma ilima lim. current accuracy rel to progr. val. 20 to 50ma active np, rp -10 10 % v iref bang up reference 1.08 1.16 1.24 v rfeed feed res. accuracy active np, rp -10 10 % rfeed h.i. feeding resistance h.i. feeding 1100 2100 ? stlc3080 11/23 symbol parameter test condition min. typ. max. unit fig. ilact feed current active active np, rp rloop = 1900 ? rdc = 1.5k ? 18 20 ma ilsby feed current stby sty, rloop = 2.2k ? rdc = 1.5k ? 13 ma i tip tip leackage current ground start 1 a i gs ring lead current ground start ring to gnd 33 ma i da reference current sourced by ttx in pin for voltage drop programming v ttx = 0v -70 -60 -45 a detectors i det off-hook current threshold st-by, active rel. to progr. val. 7 to 11ma -10 +10 % rel. to progr. val. 3 to 6ma -20 +20 % i det h.i. off-hook current threshold h.i. feeding 5 8 ma hys off/on hook hyst. st-by, active 15% i det ma td dialling distortion active -1 +1 ms i ll ground key current threshold i ll = i b - i a tip to ring to gnd or ring to gnd 7.5 ma igst ground start detection threshold igst = 2 ? i det ground start -10 +10 % digital interface inputs: d0, d1, d2, r0, r1, csin, csout vih input high voltage v dd = 3.3v 2 v vil input low voltage v dd = 3.3v 0.8 v iih input high current 30 a iil input low current 10 a outputs: det, gdk / al vol output low voltage iol = 0.75ma; csout = low 0.5 v voh output high voltage ioh = 0.1ma; csout = low 2.4 v i oz tri-state output current csout = high -10 +10 a outputs: relr, rel0, rel1 ird current capability 40 ma vr output voltage ird = 40ma 0.6 v ird = 70ma 1.1 v iik off leakage current 3 a power supply rejection psrrc v cc to 2w port vripple = 0.1vrms 50 to 4000hz 27 db c9 psrrb vbat to 2w port vripple = 0.1vrms 50 to 4000hz 30 db c9 power consumption i cc v cc supply current h. i. feeding on-hook from 0 to 70c from -40 to 85c 1.0 1.5 ma ma sby on-hook from 0 to 70c from -40 to 85c 3.5 4 ma ma active on-hook from 0 to 70c from -40 to 85c 5.0 5.5 ma ma power down from 0 to 70c from -40 to 85c 1.0 1.5 ma ma electrical characteristics (continued) stlc3080 12/23 note: all measurements are performed with 100pf on outputs pin and with ttl compatible voltage levels. rs 2.5k ? zac 12.5k ? za 15k ? zb 15k ? ccomp 220pf tx rs zac zb tx control interface d0 d1 d2 r0 r1 v cc agnd bgnd rel1 cac rdc 10 f crt crt 470nf iref rref 30.1k ? tip rpt1 20 ? rpr1 20 ? rpt2 30 ? rpr2 30 ? ring la vrel lb vb- vreg base crev crev 47nf vb- vring rr 600 ? d98tl313g csvr stlc3080 d0 d1 d2 r0 r1 det det csin csin iltf rdc 1.5k ? rlim rlim rth rth csvr 100nf rs2 600k ? rt2 rs1 600k ? rt1 rt relr rel0 v cc v dd rgnd v dd qext bd140 ch 220pf vbat d1 1n4448 zac1 rx rx csout csout ttxin ttx rda 10k rttx 3.75k cttx 1 f cac + res res ckring ckring pcd mode mode gdk/al gdk/al figure 4. test circuit. logic interface input timing min. max t1 100ns t2 100ns t3 250ns t4 100ns t5 100ns t6 250ns t3 t1 t2 csin d0.1.2,r0.1 d98tl312 csout det, gdk t6 t4 t5 symbol parameter test condition min. typ. max. unit fig. i bat v bat supply current h. i. feeding on-hook from 0 to 70c from -40 to 85c 0.5 1.0 ma ma sby on-hook from 0 to 70c from -40 to 85c 2.5 3.5 ma ma active on-hook from 0 to 70c from -40 to 85c 4.5 5.0 ma ma power down from 0 to 70c from -40 to 85c 0.5 1.0 ma ma i dd v dd supply current any operating mode 100 320 a electrical characteristics (continued) stlc3080 13/23 the flow-chart in fig.a1 describes the sequence of state machine supervising the stlc3080 op- eration when the control is set for active mode, d0 d1 d2= 1 x x. the state machine is a synchronous sequential circuit internally clocked by a free running oscilla- tor ; the ringing frequency applied at the ckring input is used to generate the long time delay wtime=128xckring necessary for proper op- eration as further described. external control is supposed to be set for active mode : d0 d1 d2= 1 x x. oh-hi : line status flag , set high when off-hook condition is detected in high impedance feeding; it differs from ohk because it?s sensitive to the longitudinal current. ohk: line status flag , set high when off-hook condition is detected in stand-by or in active mode; it differs from oh-hi for its immunity to lon- gitudinal current . dly: time-out flag, it is set high to resume, with a given delay, the high impedance feeding when an on-hook condition (ohk=low) is detected in stand-by or active state. 1) note that in this section the word "mode" has been used to indicate the operating status set with d0, d1 and d2 pin: the word "state" has been used to indicate an internal status of the finite state machine. flow-chart description h) a reset condition, generated at power on or setting res pin low, forces a power-down condition. a) high impedance feeding is entered after the active mode word is set and its maintained un- til an off-hook condition is detected (oh- hi=high) ; in this case stand-by state entered. b) stand-by state is set to perform a validity check of the off-hook status of the line before entering active state. if it is confirmed (oh=high), immediately active state is en- tered. if not , stand-by state remains set for a time period wtime generated through a counter that times out after 128 x ckring ; dly=high signals the state machine the time out to re- sume the high impedance feeding. an ohk = high detected during wtime will im- mediately enter active state. c) active state is set for conversation and det=low signals to the controller the off-hook condition of the line. the status remains set as long as ohk=high (off-hook). d) when ohk=low is detected (on hook), det is immediately set high whereas active state is maintained for the period wtime; when it ex- pires dly is set high and high impedance feeding is resumed. if, during wtime, ohk=high is detected off hook), the state is returned to c) , i.e. active with det=low. e) ringing mode is set when d0 = d1 = 0 and d2 = 1. after ring trip detection the slic is automat- ically set in active state (reverse or normal po- larity according to d2 value set before ringing mode). ring trip detection is indicated by det pin: when it happens the sw must remove the ringing mode word (001) and set the active mode word (100). f) on-hook tx mode is selected when d0 = 0, d1 = 1 and d2 = x. after off hook detection the slic is automat- ically set in active state. appendix a stlc3080 14/23 figure a1. stlc3080 15/23 stlc3080: allowed rfeed values vs. ilim the stlc3080 device has been designed in or- der to fit in a small smd package (tqfp44). this target has been achieved by using a dedicated circuit for power management based on one ex- ternal transistor (qext). the particular power management circuit adopted allows to define the percentage of power dissi- pated on the slic itself and on the qext. the sharing percentage is defined by the rfeed value, in particular the higher is rfeed, the higher is the percentage dissipated on the slic. rfeed represents the dc feeding impedance at tip/ring terminals (including 2xrp) when the slic is in the resistive feed region of the dc characteristics. since the max. power dissipation inside the slic is limited it is important to know which value of rfeed can be implemented without exceeding the max power allowed in the slic. in order to define the allowed rfeed values sev- eral other parameters should be considered, in particular: pdslic: max allowed power dissipation on slic, two val- ues are considered: 1.1w for 70c t amb application; 0.9w for 85c t amb application; pdqext: max allowed power dissipation on qext, three val- ues are considered: 1.0w 1.5w 2.0w these values depend on the package and the as- sembly of the qext. ilim: programmed constant current value, continuous variations are considered from 20ma to 50ma. vbat: battery voltage, three values are considered: 48v 54v 62v the following diagrams show the allowed rfeed values depending on the above parameters. three diagrams are shown each one for a particular bat- tery (vbat = -48v, -54v, -60v). in each diagrams you can find an upper and a lower limits for the rfeed value: the upper limit is defined by one of the two b1, b2 curves. b1 is the limit when max. power on slic is equal to 0.9w (t amb = 85c) b2 is the limit when max. power on slic is equal to 1.1w (tamb = 70c) the lower limit is defined by one of the three a1, a2, a3 curves. a1 is the limit when max. power allowed on qext is equal to 1.0w a2 is the limit when max. power allowed on qext is equal to 1.5w a3 is the limit when max. power allowed on qext is equal to 2.0w figure b1. rfeed allowed values vs. ilim (vbat = -48v). appendix b stlc3080 16/23 figure b2. rfeed allowed values vs. ilim (vbat = -54v). figure b3. rfeed allowed values vs. ilim (vbat = -60v). example: considering the following parameters: vbat = -48v, max tamb = 70c, ilim = 25ma, qext able to dissipate 1w, the possible values of rfeed can be found in fig. 1 and are limited by the b2 curve (upper limit) and the a1 curve (lower limit). in particular considering the ilim = 25ma the rfeed allowed range will be: 500 ? < rfeed < 1700 ? stlc3080 17/23 appendix c stlc3080 test circuits referring to the applica- tion diagram shown in figure 4 and using as exter- nal components the typ. values specified in the "external components", find below the proper configuration for each measurement. tip ring tx rx vl vrx 300 300 stlc 3080 g42 = 20lo g ( vl / vrx ) test circuit figure c1. receive gain. tip ring tx rx rp rp vl vrx 300 300 stlc 3080 thl = 20lo g ( vrx /vtx ) vtx test circuit figure c2. thl trans hybrid loss. tip ring tx rx vtx stlc 3080 g24 = 20lo g ( 2vtx / e ) 600 test circuit e figure c4. transmit gain. tip ring tx rx rp vl vtl vrx 300 300 stlc 3080 t/l = 20log (vl / vtl ) test circuit figure c3. t/l transversal to longitudinal conversion tip ring tx rx stlc 3080 2wrl = 20lo g ( e / 2vs ) e vs 600 1000 1000 test circuit figure c6. 2w return loss. tip ring tx rx vac 300 300 stlc 3080 l/t = 20log ( e / vac ) 10uf e test circuit figure c5. l/t longitudinal to transversal conversion. stlc3080 18/23 tip ring tx rx vtx stlc 3080 v4w p = 20lo g ( vtx / 0.775v ) 600 test circuit figure c7. idle channel psophometric noise at tx port. tip ring tx rx vtx stlc 3080 v2w p = 20lo g ( vl / 0.775v ) 600 vl test circuit figure c8. idle channel psophometric noise at line terminals. tip ring tx rx stlc 3080 psrrb = 20lo g ( vnvbat / vl ) 600 vl psrrc = 20lo g ( vnvcc / vl ) vbat/vcc vn = 0.1vrms test circuit figure c9. psrrc = power supply rejection v cc to 2w port psrrb = power supply rejection v bat to 2w port stlc3080 19/23 in ringing mode the stlc3080 provides: - relay driver capability (relay is synchronized with low level of ckring) - ring-trip detection the monitor of the line state is performed by sensing the line current converted into a voltage drop across the rr resistor connected in series to the line. this voltage is read via rs1and rst2 input pins of a differential stage that identifies, during the ringing phase, the on/off hook state of the line (see fig. d1). the ring-trip condition is detected by sensing the dc component of the line current, rejecting the ac component. with rr = 600 ? the ring- trip threshold is: iline>7.5ma when the ring-trip is detected, the stlc3080: - deactivates the ringing relay relr (if ckring is low); - indicates the ring-trip detection by setting det=low; - forces the active state. the information at relr and det pins is lached and it doesn?t change opening the current loop. to reset the latched informations the active or on-hook transmission mode have to be entered (in general changing the device mode the latched information is removed). although the ring-trip detection sets det to signal the line status, there is a substantial difference re- spect to the on/off-hook detection. in ringing mode on-hook condition, an ac current is present on the line. the ring-trip detector rejects the ac component by integrating the line current: the de- tection threshold can be reached only if the line current has a dc component higher than the threshold. as a consequence the response is not immediate (as it is for off-hook in active state): it takes an amount of time that is dependent on the dc current value (i.e. on the line length). the ac rejection and the delay depend on the crt ca- pacitor value (see fig.d1). when the voltage on the capacitor exceeds 3v, the ring-trip is detected (see fig.d3). crt should be selected in order to avoid that during one half sinewave cycle, in on-hook, its voltage vcrt exceeds 3v (ring-trip threshold). the mini- mum value of crt can be carried out with the fol- lowing formula: ccrt > 6 f/fring with fring = 20hz, you obtain a ccrt = 390nf. when the crt capacitor is selected, it must be considered that it is also used for the rejection of the common mode current. in this case the mini- mum value of the crt capacitor can be carried out with the following formula: ccrt > (ip/fl) ? 560 f where ip is the peak of the longitutudinal current and fl is the frequency of this current. with ip = 25ma @ fl = 50hz you obtain 330nf. for this reasons the suggested value for typical central office application is 470nf. appendix d ringing mode and ring trip detection rs1 rs2 rr vb crt i line i crt vcc i th =7.5ua(typ) det 3volt comp i ring i ring= i line rs1/rr rs1=rs2 figure d1.ring trip circuit block diagram. stlc3080 20/23 rs1 must be connected to the positive rr; rr should be connected directly to the ringing gener- ator as it is in the figure. the ratio between rs1 and rr must be chosen considering that there is an offset current in the input stage equal to 7.5 a. this offset has been introduced to take in account the leackage current of the line. in fig.d2 is shown the relation between the crt charging current i crt and the line current i line . in the range -30 a esd - the stmicroelectronics internal quality standards set a target of 2 kv that each pin of the device should withstand in a ser ies of tests based on the human body model (mil-std 883 method 3015): with c = 100pf; r = 1500 ? and performing 3 pulses for each pin versus v cc and gnd. device characterization showed that, in front of the stmicroelectronics internaly quality standards, all pins of stlc3080 withs tand at least 1000v. one particular pin (pin n 41) withstand 500v only. the above points are not expected to represent a pratical limit for the correct device utilization nor for its reliability in t he field. nonetheless they must be mentionned in connection with the applicability of the different sure 6 requirements to stlc3080. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia ? belgium - brazil - canada - china ? czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com stlc3080 23/23 |
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